A silicon-on-insulator (SOI) structure is sometimes used in forming semiconductor devices. In a typical SOI structure, an insulator layer is formed in-between a silicon wafer. Often this insulator layer is a silicon dioxide layer referred to as a “buried oxide” layer, a “bottom oxide” layer, and/or a “BOX” layer. After the silicon is patterned, valleys or trenches remaining between the patterned silicon structures are typically filled with insulting material, such as silicon dioxide, to form shallow-trench-isolation (STI).
When the silicon is etched to pattern the silicon in an SOI structure, the vertical sidewalls of the silicon are often damaged during the process. To address this issue, manufacturers sometimes grow an oxide liner on the vertical sidewalls of the silicon. The oxide liner improves or rebuilds the sidewalls of the silicon. FIGS. 1–4 illustrate a prior process used to develop such an SOI structure having oxide liners. In FIG. 1, an initial structure 20 is shown. In this initial structure, a BOX layer 22 is formed on a silicon wafer (not shown). The silicon 24 formed on the BOX layer 22 has been patterned already in FIG. 1. The patterned silicon 24 in FIG. 1 still has a layer of pad oxide 26 thereon. A patterned layer of silicon nitride 28 is on the pad oxide layer 26. The patterned silicon nitride layer 28 was used here as a mask during the etching of the silicon 24. The pad oxide layer 26 may have been used as an etch stop layer during the development of the silicon nitride mask 28. The silicon 24 may be patterned using a reactive-ion-etching (RIE) or dry etching process, for example. Hence, this structure shown in FIG. 1 is a common initial or intermediate structure for a process of fabricating an SOI structure.
After patterning the silicon 24, an oxide liner 30 may be thermally grown on the vertical sidewalls 32 of the silicon 24, as shown in FIG. 2, for example. With the pad oxide layer 26 and/or the nitride layer 28 still present, as in FIG. 2, the oxide liner 30 is only grown on the exposed vertical sidewall portions 32 of the silicon 24. As shown in FIG. 3, after the liners 30 are formed, an insulting material 34 is deposited to fill the gaps between the patterned silicon structures 24 (i.e., for forming the STI). Such insulating material 34 may be silicon dioxide, for example. Such insulating material 34 is typically deposited using a high-density-plasma chemical-vapor-deposition (HDP-CVD) process, which may be a well known process. Subsequently, the nitride layer 28, the pad oxide layer 26, and part of the STI insulating material 34 are removed (e.g., by chemical mechanical polishing (CMP) and/or by etching) to provide an SOI structure 36, such as that shown in FIG. 4.
Recent studies have found that the prior method shown in FIGS. 1–4 yields a structure where the liner 30 exerts stress on the silicon 24 at the interface 38 of the silicon 24 and the BOX layer 22. Typically, such stress is highest at the edges of the silicon 24. The stress exerted on the silicon 24 may be upward along the sidewalls 32 and compressive towards the channel region. This stress is believed to be caused by the thermal growth process for forming the oxide liners 30 because the growth will occur in all directions, including vertically along the silicon sidewalls 32. As the oxide liners 30 are grown (see e.g., FIG. 2), the growth often extends into the BOX layer 22 (at the interface of the silicon 24 and the BOX layer 22). This may cause lifting of and/or lifting stress on the silicon 24 at the liner 30 (i.e., at the edge of the silicon 24). This is illustrated in FIG. 5. In FIG. 5, the silicon edge has been lifted and a “bird's beak” 40 of insulating material has formed under the edge of the silicon 24 at the interface 38. This bird's beak portion 40 keeps the silicon 24 under strain, as illustrated by the arrows 42 in FIG. 5, which is usually undesirable. Hence, a need exists for ways to reduce or eliminate this unwanted strain on the silicon 24 of the SOI structure 36.